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NJU6573
Preliminary
16COM x 100SEG 1/16 Duty BITMAP LCD Driver
! GENERAL DESCRIPTION The NJU6573 is a 16-common x 100-segment bitmap LCD driver to display graphics or characters. It incorporates 16 common driver circuits and 100 segment driver circuits. The NJU6573 can display a 16 x 100 dots graphic or 2-line by 20-character (5 x 7 dots per character). In addition, the NJU6573's useful functions meet a wide range of applications. PACKAGE OUTLINE
NJU6573
! FEATURES : 16-common and 100-segment : 1/5 bias : Shift clock max. 2MHz : CR oscillation with external resistor and capacitor, or external oscillation signal input. Programmable Contrast Control:16-steps Electrical Variable Resister (EVR) Voltage Tripler and bleeder resistance on-chip. Operating Voltage : VDD=2.4~3.6V C-MOS Technology : Substrate : P Package : LQFP144 20.0mm x 20.0mm t=1.7mm(Max) 0.5mm pitch LCD driving circuit Bias Ratio Serial Data Transfer Oscillator
Ver.2009-07-28
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NJU6573
Preliminary
! BLOCK DIAGRAM
COM0 COM0COM15
VDD VSS TESTIN2 VCI C1P C1N C2P C2N VDCOUT DCOUT VDCIN
VDD VDD VDD
SEG0SEG99 SEG0SEG99
Chip
V0 CVON CVOFF VDD
COM DRIVER CIRCUIT(16)
VDD
V0 SVON SVOFF VDD
SEG DRIVER100
VOLTAGE CONVERTER
VDD
COM CONTRORER
LINE SELECT
VREF REGULATORE VREG V0
V0 SVON VREG VDD
V1 V2 V3 V4
VSS
LCD DRIVER VOLTAGE CIRCUIT
SVOFF
CVON
LATCH BLOCK(10016
CVOFF
VDD
OSC INH INH RST RST
VDD
OSCILLATOR CIRCUIT
BOOST EXOSC
LOGIC CIRCUIT
VDD
CS CS SCL SCL SI
VDD
IF
SERIAL DATA CLOCK DISPLAY DATA
SHIFT REGISTER(105)
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Ver.2009-07-28
NJU6573
Preliminary
! PAD LOCATION
108 COM91 107 73 COM56 72 71 70 69 68 67 66 SEG99 V4 V3 V2 V1 V0 VREG VREF N.C VDCIN VDCOUT C2P C2N C1P C1N VCI TESTIN VSS TESTIN2 BOOST VDD EXOSC OSC INHb SI SCL CSb RSTb TESTOUT 24 25 33 10 11 12 13 14 15 COM15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 SEG20 34 35 SEG19 36 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
104
102 101
106 105
103
100 99 98 97 96
94 93 92
85 84
91
90 89 88
87 86
83
82 81
80
79 78
77
76
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
SEG92
95
NJU6573
COM0
8 9
1
2
3 4 5
6 7
Ver.2009-07-28
SEG0
75 74
SEG55
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NJU6573
Preliminary
! TERMINAL DISCRIPTION
No. 136 131 122 123 139 125 126 121 120 119 118 117 133 129 130 127 128 143 142 140 Pad Name VDD VCI VREG VREF INHb VDCIN VDCOUT V0 V1 V2 V3 V4 VSS C1P C1N C2P C2N RSTb CSb SI Function Power Supply: (2.4V-3.6V) Booster voltage input terminal(MAX:3.3V) Voltage Regulator Output Regulator base voltage input terminal for VREG output (MAX:3.3V) Display ON or OFF "High"=Display ON, "Low"=Display OFF, Voltage Regulator Input Booster voltage output terminal (Internal Booster Circuit Output Terminal)
Bias V0 V1 V2 V3 V4 VSS GND Terminal VSS =0V Capacitor Connect Terminal for Voltage Booster Reset When RSTb is "Low", Latch Circuit is Reset. Chip Select When CSb is "Low", Data can be read in. Serial Data Input Terminal
141
SCL
Serial Clock Input Terminal (Max: 2MHz)
138 137
OSC EXOSC
OSC: External Resistor and Capacitor Connect Terminal for CR Oscillation, or External Clock Input Terminal. EXOSC: "High"=External Clock Input, "Low"=CR Connect,
1-16 17-116
COM0-COM15 SEG0-SEG99
Common Driver Outputs Segment Driver Outputs Voltage Booster ON or OFF "High"=Voltage Booster ON, "Low"=Voltage Booster OFF, BOOST Internal Booster Internal Regulator Circuit L OFF OFF H ON ON Test Terminal (Keep TESTIN-Vss short Test2 Terminal (Keep TESTIN2-Vss short) Test Out TerminalThere is open Terminal electrically There is open Terminal electrically
135
BOOST
132 134 144 124
TESTIN TESTIN2 TESTOUT N.C.
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Ver.2009-07-28
NJU6573
Preliminary
! FUNCTION DESCRIPTION
(1) Shift Resister 105 bits resister (2) Latch Circuit Data stored in display data register is assigned to the corresponding SEG/port. (3) Segment Driver Basing on display data, segment drivers output LCD SEG driving signal. (4) Common Driver Common drivers output LCD COM driving signal. (5) Voltage Booster NJU6573 with a built-in Voltage Booster. The internal voltage booster generates up to 3xVCI voltage(Input:VCI Terminal, Output: VDCOUT Terminal). The boost voltage VDCOUT must not exceed 10.0V(VCIx3 10V), otherwise the voltage stress may case a permanent damage to the LSI. When using the internal LCD power supply, connect the VDCOUT and the VDCIN. The VREF voltage is tripled to obtain the VREG voltage.(VREFx3=VREG)
Ver.2009-07-28
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NJU6573
Preliminary
(5) Bleeder Resistance Each LCD driving voltage (V1, V2, V3, V4) is LCD driving high voltage input to the V0 Terminal, generated by the E.V.R and high impedance bleeder resistance. LCD driving voltage generation circuit generates LCD driving bias voltages V0, V1, V2, V3 and V4. VREG, V0, V1, V2, V3 and V4 terminals requires external capacitors for bias voltage stabilization for display quality. These values of capacitors should be fixed in accordance with evaluation in the application. LCD Driving Voltage vs Duty Ratio Duty Ratio 1/16 Power supply Bias 1/5 VLCD V0- VSS
VLCD is the maximum amplitude for LCD driving voltage.
VDCOUT VDCIN VREF
From Voltage booster Internal NJU6573
Regulator
VREG 011.25K V0 4K V1 4K V2 4K V3 4K V4 4K V4 V3 VLCD V2 V1 V0 E.V.R(16Steps)
Vss
Vss
Fig Bleeder Resistance
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Ver.2009-07-28
NJU6573
Preliminary
(6) Oscillator circuit The oscillator consists of an external capacitor and an resistor. It generates clock signal for LCD driving. When use external clock, input the clock signal to OSC.(EXOSC Terminal is "High" when use external clock) VDD
NJU6573
200K OSC 100pF (fOSC=30.8kHz TYP)
Fig OSC Circuit
(6-1) Relation between Oscillation frequency and Frame frequency Frame frequency = fosc / 384 Set the oscillation frequency to obtain the frame frequency.
Ver.2009-07-28
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NJU6573
Preliminary
(7) Input Data Format and Timing Data format is shown below. When the CSb terminal goes to "L" at SCL terminal "H", I/F is data input. Data fetched at SCL rising edge. In case of entering less then 105-bit data(Display Data:100bit, COM select data:4bit,E.V.R set data:1bit), Malfunction. In case of entering over then 105-bit data, valid data is last 105-bit data. (7-1) 1/16Duty
CSb SCL SI
D1 D2 D3 D99 D100 0 0 0 EVR
EVRThe Bit set E.V.R or COM "L": COM select data "H": E.V.R. select data
Display Data(1-100)
COM0 select data
EVR set
CSb SCL SI
D101 D102 D103 D199 D200 0 0 0 1 EVR
Display Data(101-200) CSb SCL SI
D201 D202 D203 D299 D300 0
COM1 select data
EVR set
0
1
0
EVR
Display Data(201-300)
COM2 select data
EVR set
CSb SCL SI
D301 D302 D303 D399 D400 0 1 1 EVR
Display Data(301-400)
COM3 select data
EVR set
CSb SCL SI
D1501 D1502 D1503 D1599 D1600 1 1 1 1 EVR
Display Data(1501-1600)
COM15 select data
EVR set
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Ver.2009-07-28
NJU6573
Preliminary
CSb SCL SI 108 107 106 105 104 103 4 3 2 1
Before CSb are raised, data on 106 bits and more. (Invalid)
Before CSb are raised, data on 105 bits.(valid)
In case of entering over then 105-bit data
(7-2) Display OFF (INHb) When INHb is "H", display is ON, and when INHb is "L", display is off. When INHb="L" All segment and common terminal output Vss (7-3) Voltage Booster Circuit Select (BOOST terminal) Voltage Booster ON or OFF
BOOST Voltage Booster Circuit Regulator Circuit VLCD operation supply H ON ON Internal Booster Circuit using L OFF OFF External VLCD power supply Input
(7-4) Reset(RSTb) When RSTb is "Low", latch circuit is reset. But, Display ON/OFF can not be reset (control).
(7-5) Supply Voltage Sequence Supply voltage ON Display OFFINHb="L"
Reset (Over 1.3msec RSTb="L")
Display Data write
Wait time: 100msec Display ON (INHb="H")
Fig
Supply Voltage Sequence
Ver.2009-07-28
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NJU6573
Preliminary
(8) Instructions The NJU6573 incorporates E.V.R register(high). Instruction code as show below. Table. Table of Instructions Instruction Electrical Voltage Resistor Explanation When the CSb terminal rising edge eve one bit is High, Data fetched at SCL rising edge. In case of entering less then 2-5bit data valid.
EVR set SCL SI
* * * * * C3 C2 C1 C0 1
CSb
*: Even only 5 clock can set E.V.R if the last bit is "1".
Don't care
Contrast Control instruction which adjusts the contrast of the LCD is executed when the code "1" is written into EVR and the codes of C3 to C0 are written into 2 to 5bit as shown below. The contrast of LCD can be adjusted one of 16 voltage-stages by setting this 4-bit register. See below "how to adjust the Contrast of LCD". Set the binary code "1,1,1,1" when contrast adjustment is unused.
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VLCD voltage (Spec) VOUT x 0.640 VOUT x 0.656 VOUT x 0.672 VOUT x 0.690 VOUT x 0.708 VOUT x 0.727 VOUT x 0.748 VOUT x 0.769 VOUT x 0.792 VOUT x 0.816 VOUT x 0.842 VOUT x 0.870 VOUT x 0.899 VOUT x 0.930 VOUT x 0.964 VOUT x 1.000
Ex.) VLCD voltage by VOUT=8.4V 5.376 5.508 5.647 5.793 5.947 6.109 6.280 6.462 6.653 6.857 7.074 7.304 7.551 7.814 8.096 8.400
VLCD=VREG x 20 / (31.25-0.75 x M) M: Contrast control resistor = 0-15
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Ver.2009-07-28
NJU6573
Preliminary
*
Input Data v.s output
COM
Ver.2009-07-28
- 11 -
NJU6573
Preliminary
! ABSOLUTE MAXIMAM RATINGS
PARAMETER Supply Voltage 1 Supply Voltage 2 Supply Voltage 3 Input Voltage Operating Temp. Storage Temp. Dissipation Power Note-1) SYMBOL VDD,VREF VCI VDCIN, V0 V1~V4,VREG Vt Topr Tstg RATINGS -0.3 ~ +7.0 -0.3 ~ +10.5 -0.3 ~ +10.5 -0.3 ~ VDD+0.3 -40 ~ +105 -55 ~ +125 UNIT V V V V C C (VSS=0V, Ta=25C) CONDITIONS VCI Terminal Note-4) VDCIN, V0, V1~V4 ,VREG Terminal INHb, CSb, SCL, SI, RSTb, OSC, BOOST EXOSC,TESTIN,TEST2, applicable.
Note-2) Note-3) Note-4)
The power dissipation is value mounted on 4 layer glass PD 1000 mW epoxy board in size 76.2mm x 114.3mm x 1.6tmm Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used within the range specified in the DC electrical characteristics, or the electrical stress may cause mulfunctions and impact on the reliability. To stabilize the LSI operation, place decoupling capacitors between VDD-VSS, VCI-VSS and between VDCIN-VSS. All voltages are relative to VSS = 0V reference.The following relationship shall be maintained. VDCIN V0 VDD>VSS, and VSS =0V When voltage booster circuit, need condition of 10V VCIx3.
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Ver.2009-07-28
NJU6573
Preliminary
ELECTRICAL CHARACTERISTICS
*
DC characteristics SYMBOL PARAMETER
VDD VCI VDCIN VIH1
Terminal
VDD VCI VDCIN CSb, SCL, SI, RSTb, OSC,BOOST INHb, EXOSC COM0COM15 SEG0SEG99 CSb, SCL, RSTb, INHb, BOOST, EXOSC VDD
CONDITIONS
Power Supply 1 Power Supply 2 Power Supply 3
(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +105C) MIN TYP MAX UNIT Note 2.4 3.6 V 2.4 3.3 V 5 3.6 10.0 6
0.8 VDD VSS VDD 0.2 VDD 20 20
V V kOhm kOhm A 7 7
Input voltage 1 VIL1 Driver-on(COM) Resistance Driver-on(SEG) Resistance Input leakage current RCOM RSEG
Id=1A(COM Terminal) VO=V0,VSS, V1,V4 Id=1A(SEG Terminal) VO=V0,VSS, V2,V3 VIN=0~VDD
-
ILI
-1.0
VDD=VCI=3V, VREF=2.7V, fosc=30.8kHz, Checker Display ON, Booster ON, Ta=25C E.V.R: "1111" SEG/COM open VDCOUT/VDCIN connect
-
1.0
IDD1 Operating Current
-
30
50
A mA A mA V
8
ICI IDD1 ICI V0 V1 V2 V3 V4
VCI VDD VCI V0 V1 V2 V3 V4
7.8 6.2 4.6 3.0 1.4
1.5 90 1.7 6.4 4.8 3.2 1.6
2.0 150 2.2 8.0 6.6 5.0 3.4 1.8
fOSC=184.8kHz Other condition same as IDD1 VREG =8.0V E.V.R: "1111"
8
LCD operating voltage
Bleeder resistance RB=V0/IB RB: Bleeder resistance 5 IB: Bleeder resistance Current
RB
VREG
VREG =8.0V E.V.R: "1111", Ta=25C
14.0
20.0
26.0
kOhm
Booster output voltage
VOUT
VDCOUT
OSC Frequency
fOSC
OSC
VCI=3.3V, Ta=25C fOSC=30.8k-184.8kHz, BoosterON(COM/SEGopen) VDCOUT between VDCIN connect VDD =3V, Ta=25C, ROSC= 200kOhm COSC= 100pF ROSC= 30kOhm Other condition same as fOSC External input
9.0
9.5
-
V
25.3 151.8 25.3 66
30.8 184.8 VREF x 3 0.05 0.5
36.3
kHz
217.8 217.8 566 VDD VREF x 3 x 1.02 0.10 0.8
External clock Operating Frequency Operate Frame Frequency range VREF input voltage Regulator output voltage Dropout Voltage VDCIN Current
fCP Fr VREF VREG Delta VIO IOUT
OSC COM VREF VREG VDCIN-VREG VDCIN
kHz Hz V V V mA 9
VDCIN =10V, VREF=3V, (COM/SEG open) VDCIN=9V, VREF=3.6V, IO=-200A VDCIN=9.0V, VREF=2.7V E.V.R: "1111", INHb=0 Ta=25C (COM/SEG open)
1.0 VREF x 3 x 0.98 -
Ver.2009-07-28
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NJU6573
Preliminary
Note-5) When voltage booster circuit using, need condition of VDCOUT10V Note-6) Condition of VDCIN Voltage: 10VVDCINVREF x 3+ 0.6 Note-7) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 , V3 or V4 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals.
3V
NJU6573
A
VDD
Vss
Note-8) If input voltage is outside of the spec, when operating current increase. Input level must be condition "H" or "L". This mesurement condition is SI terminal between VDD short. Note-9) Frame frequency vs OSC is as the show relation between oscillation frequency and Frame frequency page7. Example characteristic) Condition C=100[pF] R=from 27k[ohm] to 200k[ohm] Temperature=25[C] The following graph is the data of example sample, so without guarantee.
fosc vs Resistance (C=100pF)
VDD=3V, Ta=25
220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
fosc [kHz]
Resistance [kohm]
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Ver.2009-07-28
NJU6573
Preliminary
*
AC characteristics PARAMETER "L" Level Clock Pulse Width "H" Level Clock Pulse Width Data Setup Time Data Hold Time CSb Setup Time CSb Hold Time CSb"H" Level Pulse Width Rising Time Falling Time
*
SYMBOL tWCLL tWCLH tDS tDH tCS tCH tWCH tr tf
(VDD=V0=2.4 to 3.6V, VSS=0V, Ta=-40 to +105C) CONDITIONS MIN TYP MAX UNIT Note 230 ns 230 30 30 50 50 250 20 20 tWCH ns ns ns ns ns ns ns ns
Input Timing
CSb tCS tWCLH tWCLL tf tr tCH
SCL tDS SI tDH
*
Input condition when hardware reset circuit is used PARAMETER Reset Input "L" Level Width Reset Rising Time Reset Falling Time tfRS VIH RSTb VIL SYMBOL tRSL trRS tfRS tRSL trRS CONDITIONS OSC=30.8kHz18% OSC=184.8kHz18% MIN 1.3 0.3 TYP (Ta=-40 to +105C) MAX UNIT ms ms 100 ns 100 ns
Ver.2009-07-28
- 15 -
NJU6573
Preliminary
LCD Operating Wave Form
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
COM15 SEG 0 1 234
1
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
2
3
4
15 16
1
2
3
4
15 16
1
2
3
COM0
COM1
COM2
* * * *
* * * *
COM3
V0 V1 V2 V3 V4 VSS
SEG0
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
SEG1
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Ver.2009-07-28
NJU6573
Preliminary
Input and Output Circuit
VDD
VDD
IN
IN
VSS
VSS
RSTb, CSb, SI,SCL
OSC, EXOSC, INHb, TESTIN, BOOST, TESTIN2
V0
Vss OUT V0
Vss
SEG0~SEG99, COM0~COM15
Ver.2009-07-28
- 17 -
NJU6573
Preliminary
APPLICATION CIRCUIT
VDD
C1
VCI
VDD VSS VCI (VCI x3 10V) VREF (VREF x3 (VDCIN-0.1V) ) C1P C1N C2P C2N VDCOUT
C2 C3 C4
C5
C6 C7 C8 C9 C10 C11 C12
VDD
VDCIN VREG V0 V1 V2 V3 V4
BOOST TESTIN, TESTIN2 EXOSC
R1 C13
OSC RSTb INHb CSb SI SCL
CPU
NJU6573
Reference value R1 C13 C4,5,6,7 C1-C3,C8-C12
200k 100pF 1.0-4.7 0.1-1.0
F F
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Ver.2009-07-28
NJU6573
Preliminary
VDD
C1
VDD VSS VCI VREF C1P C1N C2P C2N VDCOUT
C2 C3 C4 C5 C6 C7
VDD
VREG 10V
VDCIN VREG V0 V1 V2 V3 V4
BOOST TESTIN, TESTIN2 EXOSC
OSC RSTb INHb CSb SI SCL
CPU
NJU6573
Reference value C2 1.0-4.7 C1,C3-C7 0.1-1.0
F F
Ver.2009-07-28
- 19 -
NJU6573
Preliminary
VDD
C1
VDD VSS VCI
C2
VREF C1P C1N C2P C2N VDCOUT
C3 C4 C5 C6 C7 C8 C9
VDD
VDCIN 10V
VDCIN VREG V0 V1 V2 V3 V4
BOOST TESTIN, TESTIN2 EXOSC
OSC RSTb INHb CSb SI SCL
Reference value C3,4 1.0-4.7 C1,C2-C9 0.1-1.0
CPU
NJU6573
F F
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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Ver.2009-07-28

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